The present invention relates to a semiconductor device and a technique of manufacturing the same and more particularly to a technique which is useful for a semiconductor device having a high voltage MISFET and a resistance element over a semiconductor substrate and a technique of manufacturing the same.
As a technique of electrically isolating neighboring semiconductor elements, the STI (Shallow Trench Isolation) technique has been known where a trench is made in an element isolating region of a semiconductor substrate and an insulating film is buried in it. In order to make such an element isolating trench, first the semiconductor substrate is etched to make a trench and then a silicon oxide film whose thickness is larger than the depth of the trench is deposited on the substrate. Then, the silicon oxide film portion protruding from the trench is removed by chemical mechanical polishing, so that some of the silicon oxide film is left inside the trench and the trench surface is flattened.
The size a semiconductor element is optimized according to its purpose or functionality and in fact, various semiconductor elements of different sizes are mounted on a semiconductor substrate. For example, it is common that a MISFET which operates at high supply voltage (hereinafter called a high voltage MISFET) is larger than a MISFET which operates at low supply voltage (hereinafter called a low voltage MISFET) and also the gate insulating film of the former is thicker than that of the latter. Furthermore, generally speaking, passive elements such as resistance elements and capacitors are larger than low voltage MISFETs. In addition, since integrated circuits vary in integration density of semiconductor elements according to the purpose or functionality, it is common that some areas of an actual semiconductor substrate are densely dotted with semiconductor elements and other areas of it are sparsely dotted with semiconductor elements.
On the other hand, the size of a semiconductor element isolating trench is determined by the semiconductor element size and density. This means that in an actual semiconductor substrate, there are element isolating trenches of different sizes and some areas are densely dotted with element isolating trenches and other areas are sparsely dotted with element isolating trenches.
However, in the conventional process of making element isolating trenches, the following problem arises: when plural trenches of different sizes are made in a semiconductor substrate and then a silicon oxide film is deposited on them and their surfaces are polished by chemical mechanical polishing, the surface of the buried silicon oxide film may become concave particularly in a large trench, like a dish (this phenomenon is called dishing).
If such dishing should occur on a silicon oxide film in an element isolating trench, when a thin film is deposited on the semiconductor substrate at a later step, the surface flatness of the thin film deteriorates in the area above the element isolating trench. For this reason, at a next step where a photoresist film is formed over the thin film and an exposure is made, the exposure light focus range may decrease in the area above the element isolating trench, resulting in a decline in resist pattern accuracy.
As a solution to this problem, the following technique has been proposed and being applied to actual semiconductor product manufacturing processes: many small dummy active regions are made in a matrix pattern in a large element isolating region where dishing might occur considerably, in order to decrease the actual area of element isolating trenches in this region and thereby prevent dishing of the silicon oxide film.
One of the conventional techniques of making dummy active regions in a large element isolating region is described in Japanese Unexamined Patent Publication No. 2002-158278. This document discloses a technique which improves the surface flatness of the silicon oxide film and reduces the amount of data for making a photo mask for dummy active region formation by making two types of dummy active regions of different sizes in an element isolating region.
Japanese Unexamined Patent Publication No. 2002-261244 points out a problem that when a resistance element made up of a polycrystal silicon film is formed over an element isolating trench, the resistance element's width, thickness and sectional shape are different between the central part and peripheral parts of the trench due to dishing of the silicon oxide film. As a solution to this problem, the document discloses a technique which arranges dummy active regions in the vicinities of regions where resistance elements are to be formed and partitions the silicon oxide film as needed to prevent dishing.